[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

I checked with:

- Not forcing the regbank to SReg
- Adding `v_cmp_ne_u64_e64`` & supporting 64 bits sources in LowerI1Copies

It doesn't break codegen, and it no longer crashes, though we get weirdness like `v_cmp_ne_u64_e64 vcc, vcc, 0` in the output because:

  %14:sreg_32 = V_CMP_NE_U32_e64 0, $vcc_lo, implicit $exec
  $vcc_lo = COPY killed %14:sreg_32
  
  > $vcc_lo = COPY killed renamable $vcc_lo
  Identity copy: $vcc_lo = COPY killed renamable $vcc_lo
    deleted.
  renamable $vcc_lo = V_CMP_NE_U32_e64 0, $vcc_lo, implicit $exec




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959