[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

Well, I don't fully understand the condition on line 712:

  if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) 

I'm not sure what kind of copies from physical SGPRs this pass is (was) expecting to see here. I suppose an instruction like this could have two possible interpretations:

  %0:vreg_1 = COPY $sgpr0

1. Each bit of sgpr0 supplies an i1 value for the corresponding lane of the result.
2. The whole of sgpr0 is either 0 or 1, and that value should be broadcast to every lane of the result.

Stepping back a bit, it feels like you are running into problems because you have a def and a use of vcc, where one of them is implicit and the other is explicit. If def and use were both implicit or both explicit then I think things might work better. Is there a way you can change v_div_scale so that the vcc operand is explicit?


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  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959