[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

In D131959#3763894 <https://reviews.llvm.org/D131959#3763894>, @foad wrote:

> I think if you fix the COPY to refer to $vcc_lo instead of $vcc (for wave 32) then SILowerI1Copies will be happy, because $vcc_lo will satisfy the isLaneMaskReg test. But there should be no need to change the regclass of the COPY.

It's what I was initially doing, but then it crashes on Wave64:

  Process 397709 stopped
  * thread #1, name = 'llc', stop reason = hit program assert
      frame #4: 0x0000555556f066c5 llc`(anonymous namespace)::SILowerI1Copies::lowerCopiesToI1(this=0x000055555f3a0ae0) at SILowerI1Copies.cpp:713:9
     710        assert(!MI.getOperand(1).getSubReg());
     711 
     712        if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) {
  -> 713          assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32);
     714          unsigned TmpReg = createLaneMaskReg(*MF);
     715          BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
     716              .addReg(SrcReg)
  (lldb) expr MI->dump()
    %7:sreg_64 = COPY $vcc
    Fix-it applied, fixed expression was: 
      MI.dump()
  (lldb) expr TII->isWave32()
  (bool) $0 = false


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https://reviews.llvm.org/D131959