[PATCH] D133067: [AMDGPU] W/a hazard if 64 bit shift amount is a highest allocated VGPR

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

The other problem each of these new instructions can create a new hazard just by itself. So we probably need to reset the iterator to a first new instruction or run recognizer on each of them.

Alternatively it can be possible to really run this earlier, from post-ra pseudo expansion.


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  https://reviews.llvm.org/D133067/new/

https://reviews.llvm.org/D133067