[PATCH] D133067: [AMDGPU] W/a hazard if 64 bit shift amount is a highest allocated VGPR

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Also we could still constrain src0 of these to a decimated RC in the finalizeLowering and keep this w/a just in case further optimizations would replace the operand. In that case this will be an extremely rare situation we hit the w/a itself. Although constraining the RC will have its own negative impact on the register allocation.


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https://reviews.llvm.org/D133067