[PATCH] D133067: [AMDGPU] W/a hazard if 64 bit shift amount is a highest allocated VGPR

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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In this case gfx90a uses v0 instead of the correct register. Swap
the value temporarily with a lower register and then swap it back.

Unfortunately hazard recognizer works after wait count insertion,
so we cannot simply reuse an arbitrary register, hence w/a also
includes a full waitcount. This can be avoided if we run it from
expandPostRAPseudo, but that is a complete misplacement.


https://reviews.llvm.org/D133067

Files:
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/test/CodeGen/AMDGPU/hazard-shift64.mir

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