[PATCH] D122918: [RISCV][CodeGen] Support Zfinx, Zdinx, Zhinx, Zhinxmin codegen
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 31 15:48:29 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/double-mem.ll:22
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: ld a2, 0(a0)
+; RV32IZFINXZDINX-NEXT: addi a0, a0, 24
----------------
This seems to be emitting an ld instruction in rv32 which is illegal.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D122918/new/
https://reviews.llvm.org/D122918
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