[PATCH] D122918: [RISCV][CodeGen] Support Zfinx, Zdinx, Zhinx, Zhinxmin codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:105
+let Predicates = [HasStdExtZdinx, IsRV32], DecoderNamespace="RV32Zdinx" in {
+def FLD_IN32X : FPLoad_r<0b011, "ld", FPR64IN32X, WriteFLD64>;
+
----------------
craig.topper wrote:
> jrtc27 wrote:
> > craig.topper wrote:
> > > Is this something that should have been in the MC layer patch?
> > No. These don't exist. From the spec:
> > 
> > ```
> > Load-pair and store-pair instructions are not provided, so transferring
> > double-precision operands in RV32Zdinx from or to memory requires
> > two loads or stores.
> > ```
> Are these expanded somewhere that I'm not seeing?
Nope, you can see them in the test output for the RV32Zdinx tests... it's just wrong. Whether these should be pseudos or we should be teaching the legaliser that f64 is legal except for loads/stores I don't know; the latter would be nice, but the interaction with spills sounds bad.

I had a similar issue downstream in CHERI-LLVM where, depending on the mode and pointer address space, there is no FLD/FSD available (when the pointer address space doesn't match the default for the encoding mode used for the current ABI). I used BuildPairF64Pseudo on loading from the address and loading from adding 4 to the address in the TableGen patterns, and added new (Cheri)SplitStoreF64Pseudo's for the store side that do SplitF64Pseudo plus storing to additional addresses. Presumably some of that could be reused if adopting that approach rather than legalisation, though if there's a nicer way without going to legalisation I'd be interested to see it as it's rather ugly (and the only user I can see of `(KILL ...)` in TableGen patterns themselves...). https://github.com/CTSRD-CHERI/llvm-project/pull/635/files, for what it's worth.


Repository:
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  https://reviews.llvm.org/D122918/new/

https://reviews.llvm.org/D122918