[PATCH] D122918: [RISCV][CodeGen] Support Zfinx, Zdinx, Zhinx, Zhinxmin codegen

Wed Aug 31 15:36:43 PDT 2022

craig.topper added a comment.

In D122918#3762574 <https://reviews.llvm.org/D122918#3762574>, @reames wrote:

> In D122918#3762537 <https://reviews.llvm.org/D122918#3762537>, @craig.topper wrote:
>
>> Assembler and disassembler support was already commited in https://reviews.llvm.org/D93298
>
> Then why does this contain what look to be MC related changes to .td files?  Looking closer, I do see that something has already landed, but there's definitely MC pieces in this.  Confusing to say the least.

Can you point to a specific example?

================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:105
+let Predicates = [HasStdExtZdinx, IsRV32], DecoderNamespace="RV32Zdinx" in {
+def FLD_IN32X : FPLoad_r<0b011, "ld", FPR64IN32X, WriteFLD64>;
+
----------------
jrtc27 wrote:
> craig.topper wrote:
> > Is this something that should have been in the MC layer patch?
> No. These don't exist. From the spec:
> 
> ```
> Load-pair and store-pair instructions are not provided, so transferring
> double-precision operands in RV32Zdinx from or to memory requires
> two loads or stores.
> ```
Are these expanded somewhere that I'm not seeing?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122918/new/

https://reviews.llvm.org/D122918