[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1012
+    const auto Reg =
+        CurDAG->getMachineFunction().addLiveIn(VCC, RI->getWaveMaskRegClass());
+    CurDAG->ReplaceAllUsesOfValueWith(
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rampitec wrote:
> Is this really needed?
Yes, otherwise a lot of tests fail with "Using an undefined physical register".


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Comment at: llvm/test/CodeGen/AMDGPU/frem.ll:2341
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_mov_b64 s[2:3], vcc
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
----------------
rampitec wrote:
> What happened here?
I think something is wrong with the way I replace `SDValue(N, 1)` in `SelectDIV_SCALE` but I'm not sure how to fix it.

The `addLiveIn` is suspicious (I can't find any ISelDAGtoDAG impl that also uses it) but without it, it crashes.


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Comment at: llvm/test/MC/AMDGPU/wave32.s:386
 
-v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX1032: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding: [0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
-// GFX1064-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
+v_div_scale_f32 v2, vcc, v0, v0, v2
+// GFX1032-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
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rampitec wrote:
> Please keep checks order so it is easy to see changes.
I didn't change the order. Do you mean the -ERR check should always be at the bottom? (e.g. change GFX1064 to GFX1032 instead of adding the -ERR suffix & checking the error message)


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Comment at: llvm/test/MC/AMDGPU/wave_any.s:201
 
-v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX10: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding: [0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
+v_div_scale_f32 v2, vcc, v0, v0, v2
+// GFX10: v_div_scale_f32_e64 v2, vcc, v0, v0, v2 ; encoding: [0x02,0x6a,0x6d,0xd5,0x00,0x01,0x0a,0x04]
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rampitec wrote:
> Ditto.
Is the check order the issue or the encoding? Encoding looks good to me


Repository:
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  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959