[PATCH] D132529: [AArch64] Fix sched model for tsv110

[Allen zhong via Phabricator via llvm-commits]

Allen updated this revision to Diff 455174.
Allen edited the summary of this revision.
Allen added a comment.

Split the load/store capable into two pipelines out as there is only one store pipeline capable


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132529/new/

https://reviews.llvm.org/D132529

Files:
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s

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