[PATCH] D132529: [AArch64] Fix sched model for tsv110
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 05:46:19 PDT 2022
Allen added a comment.
In D132529#3745010 <https://reviews.llvm.org/D132529#3745010>, @dmgreen wrote:
> If there is only one load/store pipeline capable of stores, would it be better to split those two pipelines out?
>
> def TSV110UnitLdSt : ProcResource<1>; // Load or Store
> def TSV110UnitLdOnly : ProcResource<1>; // Load
> def TSV110UnitLd : ProcResGroup<[TSV110UnitLdSt, TSV110UnitLdOnly]>; // Any load
>
> (I'm not sure on the syntax or the names. Hopefully you understand the meaning.)
Thanks for your idea, apply your comment.
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https://reviews.llvm.org/D132529/new/
https://reviews.llvm.org/D132529
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