[PATCH] D132482: RISCV: permit unaligned nop-slide padding emission

[Saleem Abdulrasool via Phabricator via llvm-commits]

compnerd updated this revision to Diff 454931.
compnerd marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132482/new/

https://reviews.llvm.org/D132482

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/test/MC/RISCV/align.s
  llvm/test/MC/RISCV/nop-slide.s


Index: llvm/test/MC/RISCV/nop-slide.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/nop-slide.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple riscv64 -mattr +c,-relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-NORELAX
+# RUN: llvm-mc -triple riscv64 -mattr +c,+relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-RELAX
+
+.balign 4
+.byte 0
+
+.balign 4
+auipc a0, 0
+
+# CHECK-NORELAX: 0000000000000000 <.text>:
+# CHECK-NORELAX-NEXT: 0: 00 00        	unimp
+# CHECK-NORELAX-NEXT: 2: 01 00        	nop
+# CHECK-NORELAX-NEXT: 4: 17 05 00 00  	auipc	a0, 0
+
+# CHECK-RELAX: 0000000000000000 <.text>:
+# CHECK-RELAX-NEXT:   0: 01 00        	nop
+# CHECK-RELAX-NEXT:   2: 00 01        	addi	s0, sp, 128
+# CHECK-RELAX-NEXT:   4: 00 17        	addi	s0, sp, 928
+# CHECK-RELAX-NEXT:   6: 05 00        	c.nop	1
+# CHECK-RELAX-NEXT:   8: 00           	<unknown>
Index: llvm/test/MC/RISCV/align.s
===================================================================
--- llvm/test/MC/RISCV/align.s
+++ llvm/test/MC/RISCV/align.s
@@ -41,7 +41,7 @@
 # If the +c extension is enabled, the text section will be 2-byte aligned, so
 # one c.nop instruction is sufficient.
 # C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0x2
-# C-EXT-RELAX-INST-NOT:  c.nop
+# C-EXT-RELAX-INST:  c.nop
 	bne     zero, a0, .LBB0_2
 	mv	a0, zero
 	.p2align 3
@@ -75,7 +75,7 @@
 # NORELAX-INST: addi    zero, zero, 0
 # C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
 # C-EXT-RELAX-INST:  addi    zero, zero, 0
-# C-EXT-RELAX-INST:  c.nop
+# C-EXT-RELAX-INST-NOT:  c.nop
 # C-EXT-INST: addi    zero, zero, 0
 # C-EXT-INST: c.nop
 	add	a0, a0, a1
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -354,20 +354,23 @@

 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
                                    const MCSubtargetInfo *STI) const {
-  bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
-  unsigned MinNopLen = HasStdExtC ? 2 : 4;
+  // Instructions always are at even addresses.  We must be in a data area or
+  // be unaligned due to some other reason.
+  if (Count % 2) {
+    OS.write("\0", 1);
+    Count -= 1;
+  }

-  if ((Count % MinNopLen) != 0)
-    return false;
+  // The canonical nop on RVC is c.nop.
+  if (Count >= 2 && STI->getFeatureBits()[RISCV::FeatureStdExtC]) {
+    OS.write("\x01\0", 2);
+    Count -= 2;
+  }

   // The canonical nop on RISC-V is addi x0, x0, 0.
   for (; Count >= 4; Count -= 4)
     OS.write("\x13\0\0\0", 4);

-  // The canonical nop on RVC is c.nop.
-  if (Count && HasStdExtC)
-    OS.write("\x01\0", 2);
-
   return true;
 }



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