[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec requested changes to this revision.
rampitec added a comment.
This revision now requires changes to proceed.

If we prohibit and SDTS except VCC it should be also prohibited in asm/disasm.

This is not a first instruction which can only have VCC as carry, see any VOP2be instructions, for example V_ADD_CO_U32.

It shall not have SDST at all and instead impdef VCC. Asm string operand is replaced in the real instruction depending on a wave size, see for example:

  def _dpp_w32_gfx10 :
    Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
      string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
      let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
      let isAsmParserOnly = 1;
      let WaveSizePredicate = isWave32;
    }

Plus you will need to enforce SDST encoding field to VCC for these instructions only, no need in a new SDstIsAlwaysVCC.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959