[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

In D131959#3740314 <https://reviews.llvm.org/D131959#3740314>, @rampitec wrote:

> If we prohibit and SDTS except VCC it should be also prohibited in asm/disasm.
>
> This is not a first instruction which can only have VCC as carry, see any VOP2be instructions, for example V_ADD_CO_U32.
>
> It shall not have SDST at all and instead impdef VCC. Asm string operand is replaced in the real instruction depending on a wave size, see for example:
>
>   def _dpp_w32_gfx10 :
>     Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
>       string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
>       let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
>       let isAsmParserOnly = 1;
>       let WaveSizePredicate = isWave32;
>     }
>
> Plus you will need to enforce SDST encoding field to VCC for these instructions only, no need in a new SDstIsAlwaysVCC.

Will I need to create 2 variants of the instruction, a wave32/wave64 variant (e32/e64 if I understand correctly) for this to work?
Also for the asm/disasm, do I need to change the asmparser/add tests to verify everything other than VCC is rejected in the dst?

> enforce SDST encoding field to VCC for these instructions only

How can I do this? Do I also follow the example of V_ADD_CO_U32?


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https://reviews.llvm.org/D131959