[PATCH] D131047: [AArch64] Change aarch64_neon_pmull{,64} intrinsic ISel through a new SDNode.

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4574
+      // generate a SIMD load as opposed to a GPR load followed by a fmov.
+      if (N.getValueType() == MVT::i64)
+        N = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, N);
----------------
dmgreen wrote:
> Will the type ever not be a i64?
By lowering `aarch64_neon_pmull64` to `AArch64ISD::PMULL` around line 4583 below (as suggested), the type would always be i64. So added an assert -> without `intrinsic->AArch64ISD::PMULL` lowering, the new intrinsic SDNode will be added to node list of the DAG ([[ https://github.com/llvm/llvm-project/blob/56d856c19554443677d25b91693c82dc7f35aa2c/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L1071 | code ]]) for legalization; by then the type is not i64.


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  https://reviews.llvm.org/D131047/new/

https://reviews.llvm.org/D131047