[PATCH] D131047: [AArch64] Change aarch64_neon_pmull{,64} intrinsic ISel through a new SDNode.

[Mingming Liu via Phabricator via llvm-commits]

mingmingl updated this revision to Diff 453543.
mingmingl marked 4 inline comments as done.
mingmingl edited the summary of this revision.
mingmingl added a comment.

Update include:

1. address comments
2. took the liberty to detect both lane 1 and lane 0 (previously only lane 1) so `duplane64` (as opposed to dup-from-gpr) is used for lane 0, as a small optimization.

Also at this point, `test4` in `pmull-ldr-merge.ll` is not about ldr, so `aarch64-pmull.ll` is a better place. I could send an NFC change later , so as not to frequently updating the precommit test patch ( an NFC update to precommit test is not obvious in the UI)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131047/new/

https://reviews.llvm.org/D131047

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
  llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

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