[llvm] 4854fa2 - [RISCV] Move test from setcc-logic.ll to select-const.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 14:14:51 PDT 2022
Author: Craig Topper
Date: 2022-08-16T14:08:42-07:00
New Revision: 4854fa217f4b241e0782bbea68d090e00ec245f6
URL: https://github.com/llvm/llvm-project/commit/4854fa217f4b241e0782bbea68d090e00ec245f6
DIFF: https://github.com/llvm/llvm-project/commit/4854fa217f4b241e0782bbea68d090e00ec245f6.diff
LOG: [RISCV] Move test from setcc-logic.ll to select-const.ll. NFC
Also add setne version of the test.
Add some common prefixes to reduce number of identical CHECK lines.
Added:
Modified:
llvm/test/CodeGen/RISCV/select-const.ll
llvm/test/CodeGen/RISCV/setcc-logic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 927d85d393fc..d896caba4580 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32IBT %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32IBT %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32IFBT %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32IFBT %s
; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64IBT %s
+; RUN: | FileCheck -check-prefixes=RV64,RV64IBT %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64IFDBT %s
+; RUN: | FileCheck -check-prefixes=RV64,RV64IFDBT %s
;; This tests how good we are at materialising constants using `select`. The aim
;; is that we do so without a branch if possible (at the moment our lowering of
@@ -25,133 +25,43 @@
;; the other is zero.
define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
-; RV32I-LABEL: select_const_int_easy:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_const_int_easy:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_const_int_easy:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_const_int_easy:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_const_int_easy:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_const_int_easy:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_const_int_easy:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: ret
+; RV32-LABEL: select_const_int_easy:
+; RV32: # %bb.0:
+; RV32-NEXT: ret
;
-; RV64IFDBT-LABEL: select_const_int_easy:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: ret
+; RV64-LABEL: select_const_int_easy:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = select i1 %a, i32 1, i32 0
ret i32 %1
}
define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
-; RV32I-LABEL: select_const_int_one_away:
-; RV32I: # %bb.0:
-; RV32I-NEXT: li a1, 4
-; RV32I-NEXT: sub a0, a1, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_const_int_one_away:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: li a1, 4
-; RV32IF-NEXT: sub a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_const_int_one_away:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: li a1, 4
-; RV32IBT-NEXT: sub a0, a1, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_const_int_one_away:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: li a1, 4
-; RV32IFBT-NEXT: sub a0, a1, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_const_int_one_away:
-; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, 4
-; RV64I-NEXT: sub a0, a1, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_const_int_one_away:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: li a1, 4
-; RV64IFD-NEXT: sub a0, a1, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_const_int_one_away:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: li a1, 4
-; RV64IBT-NEXT: sub a0, a1, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_const_int_one_away:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: li a1, 4
-; RV64IFDBT-NEXT: sub a0, a1, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_const_int_one_away:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, 4
+; RV32-NEXT: sub a0, a1, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_const_int_one_away:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, 4
+; RV64-NEXT: sub a0, a1, a0
+; RV64-NEXT: ret
%1 = select i1 %a, i32 3, i32 4
ret i32 %1
}
define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
-; RV32I-LABEL: select_const_int_pow2_zero:
-; RV32I: # %bb.0:
-; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_const_int_pow2_zero:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: slli a0, a0, 2
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_const_int_pow2_zero:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: slli a0, a0, 2
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_const_int_pow2_zero:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: slli a0, a0, 2
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_const_int_pow2_zero:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_const_int_pow2_zero:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: slli a0, a0, 2
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_const_int_pow2_zero:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: slli a0, a0, 2
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_const_int_pow2_zero:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: slli a0, a0, 2
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_const_int_pow2_zero:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a0, a0, 2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_const_int_pow2_zero:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 2
+; RV64-NEXT: ret
%1 = select i1 %a, i32 4, i32 0
ret i32 %1
}
@@ -323,547 +233,213 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
}
define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_eq_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_eq_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: xor a0, a0, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_eq_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: xor a0, a0, a1
-; RV32IBT-NEXT: seqz a0, a0
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_eq_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: xor a0, a0, a1
-; RV32IFBT-NEXT: seqz a0, a0
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_eq_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_eq_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: xor a0, a0, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_eq_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: xor a0, a0, a1
-; RV64IBT-NEXT: seqz a0, a0
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_eq_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: xor a0, a0, a1
-; RV64IFDBT-NEXT: seqz a0, a0
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_eq_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: xor a0, a0, a1
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_eq_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_ne_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_ne_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: xor a0, a0, a1
-; RV32IF-NEXT: snez a0, a0
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_ne_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: xor a0, a0, a1
-; RV32IBT-NEXT: snez a0, a0
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_ne_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: xor a0, a0, a1
-; RV32IFBT-NEXT: snez a0, a0
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_ne_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: snez a0, a0
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_ne_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: xor a0, a0, a1
-; RV64IFD-NEXT: snez a0, a0
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_ne_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: xor a0, a0, a1
-; RV64IBT-NEXT: snez a0, a0
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_ne_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: xor a0, a0, a1
-; RV64IFDBT-NEXT: snez a0, a0
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_ne_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: xor a0, a0, a1
+; RV32-NEXT: snez a0, a0
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_ne_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_sgt_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: slt a0, a1, a0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_sgt_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: slt a0, a1, a0
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_sgt_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: slt a0, a1, a0
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_sgt_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: slt a0, a1, a0
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_sgt_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slt a0, a1, a0
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_sgt_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: slt a0, a1, a0
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_sgt_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: slt a0, a1, a0
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_sgt_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: slt a0, a1, a0
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_sgt_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: slt a0, a1, a0
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_sgt_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: slt a0, a1, a0
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_slt_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_slt_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: slt a0, a0, a1
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_slt_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: slt a0, a0, a1
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_slt_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: slt a0, a0, a1
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_slt_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slt a0, a0, a1
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_slt_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: slt a0, a0, a1
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_slt_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: slt a0, a0, a1
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_slt_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: slt a0, a0, a1
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_slt_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: slt a0, a0, a1
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_slt_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: slt a0, a0, a1
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_sge_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_sge_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: slt a0, a0, a1
-; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_sge_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: slt a0, a0, a1
-; RV32IBT-NEXT: addi a0, a0, -1
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_sge_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: slt a0, a0, a1
-; RV32IFBT-NEXT: addi a0, a0, -1
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_sge_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slt a0, a0, a1
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_sge_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: slt a0, a0, a1
-; RV64IFD-NEXT: addi a0, a0, -1
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_sge_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: slt a0, a0, a1
-; RV64IBT-NEXT: addi a0, a0, -1
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_sge_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: slt a0, a0, a1
-; RV64IFDBT-NEXT: addi a0, a0, -1
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_sge_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: slt a0, a0, a1
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_sge_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: slt a0, a0, a1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_sle_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: slt a0, a1, a0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_sle_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: slt a0, a1, a0
-; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_sle_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: slt a0, a1, a0
-; RV32IBT-NEXT: addi a0, a0, -1
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_sle_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: slt a0, a1, a0
-; RV32IFBT-NEXT: addi a0, a0, -1
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_sle_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slt a0, a1, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_sle_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: slt a0, a1, a0
-; RV64IFD-NEXT: addi a0, a0, -1
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_sle_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: slt a0, a1, a0
-; RV64IBT-NEXT: addi a0, a0, -1
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_sle_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: slt a0, a1, a0
-; RV64IFDBT-NEXT: addi a0, a0, -1
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_sle_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: slt a0, a1, a0
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_sle_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: slt a0, a1, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_ugt_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: sltu a0, a1, a0
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_ugt_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: sltu a0, a1, a0
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_ugt_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: sltu a0, a1, a0
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_ugt_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: sltu a0, a1, a0
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_ugt_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sltu a0, a1, a0
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_ugt_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: sltu a0, a1, a0
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_ugt_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: sltu a0, a1, a0
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_ugt_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: sltu a0, a1, a0
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_ugt_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: sltu a0, a1, a0
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_ugt_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: sltu a0, a1, a0
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_ult_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: neg a0, a0
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_ult_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: sltu a0, a0, a1
-; RV32IF-NEXT: neg a0, a0
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_ult_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: sltu a0, a0, a1
-; RV32IBT-NEXT: neg a0, a0
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_ult_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: sltu a0, a0, a1
-; RV32IFBT-NEXT: neg a0, a0
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_ult_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sltu a0, a0, a1
-; RV64I-NEXT: neg a0, a0
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_ult_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: sltu a0, a0, a1
-; RV64IFD-NEXT: neg a0, a0
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_ult_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: sltu a0, a0, a1
-; RV64IBT-NEXT: neg a0, a0
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_ult_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: sltu a0, a0, a1
-; RV64IFDBT-NEXT: neg a0, a0
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_ult_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: sltu a0, a0, a1
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_ult_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_uge_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_uge_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: sltu a0, a0, a1
-; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_uge_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: sltu a0, a0, a1
-; RV32IBT-NEXT: addi a0, a0, -1
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_uge_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: sltu a0, a0, a1
-; RV32IFBT-NEXT: addi a0, a0, -1
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_uge_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sltu a0, a0, a1
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_uge_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: sltu a0, a0, a1
-; RV64IFD-NEXT: addi a0, a0, -1
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_uge_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: sltu a0, a0, a1
-; RV64IBT-NEXT: addi a0, a0, -1
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_uge_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: sltu a0, a0, a1
-; RV64IFDBT-NEXT: addi a0, a0, -1
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_uge_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: sltu a0, a0, a1
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_uge_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {
-; RV32I-LABEL: select_ule_zero_negone:
-; RV32I: # %bb.0:
-; RV32I-NEXT: sltu a0, a1, a0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: ret
-;
-; RV32IF-LABEL: select_ule_zero_negone:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: sltu a0, a1, a0
-; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: ret
-;
-; RV32IBT-LABEL: select_ule_zero_negone:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: sltu a0, a1, a0
-; RV32IBT-NEXT: addi a0, a0, -1
-; RV32IBT-NEXT: ret
-;
-; RV32IFBT-LABEL: select_ule_zero_negone:
-; RV32IFBT: # %bb.0:
-; RV32IFBT-NEXT: sltu a0, a1, a0
-; RV32IFBT-NEXT: addi a0, a0, -1
-; RV32IFBT-NEXT: ret
-;
-; RV64I-LABEL: select_ule_zero_negone:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sltu a0, a1, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
-;
-; RV64IFD-LABEL: select_ule_zero_negone:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: sltu a0, a1, a0
-; RV64IFD-NEXT: addi a0, a0, -1
-; RV64IFD-NEXT: ret
-;
-; RV64IBT-LABEL: select_ule_zero_negone:
-; RV64IBT: # %bb.0:
-; RV64IBT-NEXT: sltu a0, a1, a0
-; RV64IBT-NEXT: addi a0, a0, -1
-; RV64IBT-NEXT: ret
-;
-; RV64IFDBT-LABEL: select_ule_zero_negone:
-; RV64IFDBT: # %bb.0:
-; RV64IFDBT-NEXT: sltu a0, a1, a0
-; RV64IFDBT-NEXT: addi a0, a0, -1
-; RV64IFDBT-NEXT: ret
+; RV32-LABEL: select_ule_zero_negone:
+; RV32: # %bb.0:
+; RV32-NEXT: sltu a0, a1, a0
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_ule_zero_negone:
+; RV64: # %bb.0:
+; RV64-NEXT: sltu a0, a1, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
+
+define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {
+; RV32-LABEL: select_eq_1_2:
+; RV32: # %bb.0:
+; RV32-NEXT: xor a0, a0, a1
+; RV32-NEXT: snez a0, a0
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_eq_1_2:
+; RV64: # %bb.0:
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: addi a0, a0, 1
+; RV64-NEXT: ret
+ %1 = icmp eq i32 %a, %b
+ %2 = select i1 %1, i32 1, i32 2
+ ret i32 %2
+}
+
+define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
+; RV32-LABEL: select_ne_1_2:
+; RV32: # %bb.0:
+; RV32-NEXT: xor a0, a0, a1
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_ne_1_2:
+; RV64: # %bb.0:
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: addi a0, a0, 1
+; RV64-NEXT: ret
+ %1 = icmp ne i32 %a, %b
+ %2 = select i1 %1, i32 1, i32 2
+ ret i32 %2
+}
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 3209619b7d0e..2107c17d1ec0 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -118,24 +118,3 @@ define i1 @and_icmps_const_not1bit_
diff (i32 %x) nounwind {
%r = and i1 %a, %b
ret i1 %r
}
-
-define i32 @bar(i32 %n) {
-; RV32I-LABEL: bar:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi a0, a0, -9
-; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: bar:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -9
-; RV64I-NEXT: snez a0, a0
-; RV64I-NEXT: addi a0, a0, 1
-; RV64I-NEXT: ret
-entry:
- %cmp = icmp eq i32 %n, 9
- %a = select i1 %cmp, i32 1, i32 2
- ret i32 %a
-}
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