[llvm] 1180ed4 - [RISCV] Add more test cases for (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)). NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-16T14:08:42-07:00
New Revision: 1180ed41ee9de1804ddbfee4e6306dd20d12cd2b

URL: https://github.com/llvm/llvm-project/commit/1180ed41ee9de1804ddbfee4e6306dd20d12cd2b
DIFF: https://github.com/llvm/llvm-project/commit/1180ed41ee9de1804ddbfee4e6306dd20d12cd2b.diff

LOG: [RISCV] Add more test cases for (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)). NFC

In these test cases we do the transform, but the immediate is too
large to form an ADDI so it didn't save any instructions.

If the constant is opaque or has additional users we shouldn't do
the transform if it doesn't form an ADDI.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/select-const.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index d896caba4580..25980ab87b71 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -443,3 +443,49 @@ define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
+
+define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
+; RV32-LABEL: select_eq_10000_10001:
+; RV32:       # %bb.0:
+; RV32-NEXT:    xor a0, a0, a1
+; RV32-NEXT:    snez a0, a0
+; RV32-NEXT:    lui a1, 2
+; RV32-NEXT:    addi a1, a1, 1809
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: select_eq_10000_10001:
+; RV64:       # %bb.0:
+; RV64-NEXT:    xor a0, a0, a1
+; RV64-NEXT:    snez a0, a0
+; RV64-NEXT:    lui a1, 2
+; RV64-NEXT:    addiw a1, a1, 1809
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    ret
+  %1 = icmp eq i32 %a, %b
+  %2 = select i1 %1, i32 10001, i32 10002
+  ret i32 %2
+}
+
+define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
+; RV32-LABEL: select_ne_10001_10002:
+; RV32:       # %bb.0:
+; RV32-NEXT:    xor a0, a0, a1
+; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    lui a1, 2
+; RV32-NEXT:    addi a1, a1, 1809
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: select_ne_10001_10002:
+; RV64:       # %bb.0:
+; RV64-NEXT:    xor a0, a0, a1
+; RV64-NEXT:    seqz a0, a0
+; RV64-NEXT:    lui a1, 2
+; RV64-NEXT:    addiw a1, a1, 1809
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    ret
+  %1 = icmp ne i32 %a, %b
+  %2 = select i1 %1, i32 10001, i32 10002
+  ret i32 %2
+}