[llvm] 87e7837 - [RISCV] Add test cases to show where we inverted a fp setcc and introduced an extra xori.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-16T12:59:16-07:00
New Revision: 87e78372932e439d298c89f589e58ca05ffbc2d8

URL: https://github.com/llvm/llvm-project/commit/87e78372932e439d298c89f589e58ca05ffbc2d8
DIFF: https://github.com/llvm/llvm-project/commit/87e78372932e439d298c89f589e58ca05ffbc2d8.diff

LOG: [RISCV] Add test cases to show where we inverted a fp setcc and introduced an extra xori.

In these tests we had (sub C, (seteq X, Y)) which we converted to
the (add (setne X, Y), C-1). We don't have a FNE compare instruction
so this created an XORI to invert an FEQ instruction.

This might be a good idea since it can save a constant materialization,
but does not appear to be the intention of the original patch.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/double-select-fcmp.ll
    llvm/test/CodeGen/RISCV/float-select-fcmp.ll
    llvm/test/CodeGen/RISCV/half-select-fcmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 926bb92a29775..0afeb2f4957e1 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -241,3 +241,15 @@ define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }
+
+define i32 @select_fcmp_oeq_1_2(double %a, double %b) {
+; CHECK-LABEL: select_fcmp_oeq_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = fcmp fast oeq double %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}

diff  --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 1188201d91a9b..631fb550ff9e2 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -241,3 +241,15 @@ define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }
+
+define i32 @select_fcmp_oeq_1_2(float %a, float %b) {
+; CHECK-LABEL: select_fcmp_oeq_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = fcmp fast oeq float %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}

diff  --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index 936f590f20bfb..d83036744cc23 100644
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -241,3 +241,15 @@ define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }
+
+define i32 @select_fcmp_oeq_1_2(half %a, half %b) {
+; CHECK-LABEL: select_fcmp_oeq_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    ret
+  %1 = fcmp fast oeq half %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}