[llvm] c7e5883 - [RISCV] Minor cleanups to performSUBCombine. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 13:14:05 PDT 2022
Author: Craig Topper
Date: 2022-08-16T12:59:16-07:00
New Revision: c7e58836e8799f32f546c52e4c32ae131ecf141e
URL: https://github.com/llvm/llvm-project/commit/c7e58836e8799f32f546c52e4c32ae131ecf141e
DIFF: https://github.com/llvm/llvm-project/commit/c7e58836e8799f32f546c52e4c32ae131ecf141e.diff
LOG: [RISCV] Minor cleanups to performSUBCombine. NFC
-Rename variable NnzC -> N0C.
-Use SelectionDAG::getSetCC to reduce code.
-Use SDValue::getOperand instead of operator-> and SDNode::getOperand.
Initial steps to add another similar combine to this code.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5dd3e38cc2d41..8000c931611c4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8288,17 +8288,15 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
// NODE: constant == 0, No redundant instructions are generated.
// (sub constant, (setcc x, y, eq/neq)) ->
// (add (setcc x, y, neq/eq), constant - 1)
- auto *Nnz0 = dyn_cast<ConstantSDNode>(N0);
- if (Nnz0 && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
- const auto *CC = cast<CondCodeSDNode>(N1->getOperand(2));
- ISD::CondCode CCVal = CC->get();
- if (!Nnz0->isZero() && isIntEqualitySetCC(CCVal)) {
+ auto *N0C = dyn_cast<ConstantSDNode>(N0);
+ if (N0C && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
+ ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
+ if (!N0C->isZero() && isIntEqualitySetCC(CCVal)) {
EVT VT = N->getValueType(0);
- const APInt &ImmVal = Nnz0->getAPIntValue();
- SDValue CCInverse =
- DAG.getCondCode(ISD::getSetCCInverse(CCVal, N0.getValueType()));
- SDValue NewN0 = DAG.getNode(ISD::SETCC, SDLoc(N), VT, N1->getOperand(0),
- N1->getOperand(1), CCInverse);
+ const APInt &ImmVal = N0C->getAPIntValue();
+ CCVal = ISD::getSetCCInverse(CCVal, N0.getValueType());
+ SDValue NewN0 =
+ DAG.getSetCC(SDLoc(N), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);
return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
}
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