[llvm] 4184edc - [RISCV] (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)) fold for FP setcc.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-16T13:00:36-07:00
New Revision: 4184edc691b3d48280428ee8913c015adb66d7ec

URL: https://github.com/llvm/llvm-project/commit/4184edc691b3d48280428ee8913c015adb66d7ec
DIFF: https://github.com/llvm/llvm-project/commit/4184edc691b3d48280428ee8913c015adb66d7ec.diff

LOG: [RISCV] (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)) fold for FP setcc.

This introduce an xori in some cases. I don't believe it was the
intention of the original patch. This was an accident because
nonan FP equality compares also use SETEQ/SETNE.

Also pass the correct type to getSetCCInverse.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/double-select-fcmp.ll
    llvm/test/CodeGen/RISCV/float-select-fcmp.ll
    llvm/test/CodeGen/RISCV/half-select-fcmp.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8000c931611c..ea38077b4ab1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8291,10 +8291,11 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
   auto *N0C = dyn_cast<ConstantSDNode>(N0);
   if (N0C && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
-    if (!N0C->isZero() && isIntEqualitySetCC(CCVal)) {
+    EVT SetCCOpVT = N1.getOperand(0).getValueType();
+    if (!N0C->isZero() && SetCCOpVT.isInteger() && isIntEqualitySetCC(CCVal)) {
       EVT VT = N->getValueType(0);
       const APInt &ImmVal = N0C->getAPIntValue();
-      CCVal = ISD::getSetCCInverse(CCVal, N0.getValueType());
+      CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
       SDValue NewN0 =
           DAG.getSetCC(SDLoc(N), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
       SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);

diff  --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 0afeb2f4957e..a2344bbcfa9e 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -246,8 +246,8 @@ define i32 @select_fcmp_oeq_1_2(double %a, double %b) {
 ; CHECK-LABEL: select_fcmp_oeq_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.d a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
   %1 = fcmp fast oeq double %a, %b
   %2 = select i1 %1, i32 1, i32 2

diff  --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 631fb550ff9e..6d52d417224c 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -246,8 +246,8 @@ define i32 @select_fcmp_oeq_1_2(float %a, float %b) {
 ; CHECK-LABEL: select_fcmp_oeq_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.s a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
   %1 = fcmp fast oeq float %a, %b
   %2 = select i1 %1, i32 1, i32 2

diff  --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index d83036744cc2..5475ae4a6187 100644
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -246,8 +246,8 @@ define i32 @select_fcmp_oeq_1_2(half %a, half %b) {
 ; CHECK-LABEL: select_fcmp_oeq_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
   %1 = fcmp fast oeq half %a, %b
   %2 = select i1 %1, i32 1, i32 2