[PATCH] D131700: [AArch64] Add pattern for SQDML*Lv1i32_indexed

[OverMighty via Phabricator via llvm-commits]

overmighty added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8909
   def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
-                                      FPR32Op, FPR16Op, V128_lo, VectorIndexH,
-                                      asm, ".h", "", "", ".h", []> {
+                                      FPR32Op, FPR32Op, V64, VectorIndexH,
+                                      asm, ".h", "", "", ".h",
----------------
It looks like the second `FPR32Op` here is the cause of the failing tests, but it is required for the ISel DAG pattern below, which is the pattern of the ACLE functions mentioned in the diff summary. I doubt that we want to change the tests to fit this diff either, as instructions such as `sqdmlal.h s0, h0, v0[7]` are valid and should not result in `llvm-mc` errors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131700/new/

https://reviews.llvm.org/D131700