[PATCH] D131700: [AArch64] Add pattern for SQDML*Lv1i32_indexed

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Sounds OK to me if you can do it without changing the register types.

(I was originally unsure, for some of these it is not correct for sqadd+sqmul to be sqmla. But in this case it seems valid. The sqdmlsl does perform two saturation steps)

It may need a separate Pat so that is can generate an EXTRACT_SUBREG,  I'm not sure.  What happens if the lane index is not 0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131700/new/

https://reviews.llvm.org/D131700