[PATCH] D130993: [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:6918
   let mayLoad = 1;
+  let hasSideEffects = 1;
 }
----------------
What side effects are you worried about here?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:8600-8613
+multiclass sve_ld1rq_imm_pat<ValueType vt1, ValueType vt2, SDPatternOperator op, Instruction load_instr_imm, Instruction ptrue> {
+  def : Pat<(vt1 (op (vt1 (vector_insert_subvec (vt1 undef), (vt2 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
+        (load_instr_imm (ptrue 31), GPR64sp:$Xn, 0)>;
+  def : Pat<(vt1 (op (vt1 (vector_insert_subvec (vt1 undef), (vt2 (load (add GPR64sp:$Xn, simm4s16:$imm))), (i64 0))), (i64 0))),
+        (load_instr_imm (ptrue 31), GPR64sp:$Xn, simm4s16:$imm)>;
+}
+
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Classes like this that only contain isel patterns (i.e. are not used to define instructions) are best kept in AArch64SVEInstrInfo.td, typically next to the place they are used.

Is it possible to merge the classes like how `multiclass pred_load` is implemented? I think you'll also be able to reuse complex patterns like am_sve_regreg_lsl# rather than explicitly matching against add and shifts.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130993/new/

https://reviews.llvm.org/D130993