[PATCH] D130993: [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:6918
   let mayLoad = 1;
+  let hasSideEffects = 1;
 }
----------------
paulwalker-arm wrote:
> What side effects are you worried about here?
Checks in `N2-sve-instructions.s` fail the HasSideEffects check without this. The failing ones have the same scalar for the base and index, i.e
`# CHECK-NEXT:  1      6     0.33    *             U     ld1rqb	{ z0.b }, p0/z, [x0, x0]`
instead outputs
`# CHECK-NEXT:  1      6     0.33    *                   ld1rqb	{ z0.b }, p0/z, [x0, x0]`



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  https://reviews.llvm.org/D130993/new/

https://reviews.llvm.org/D130993