[PATCH] D130993: [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau created this revision.
MattDevereau added reviewers: paulwalker-arm, c-rhodes, dtemirbulatov, DavidTruby, peterwaller-arm, bsmith.
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Add some missing patterns for ld1rq's scalar + scalar addressing mode. Also, adds the scalar + imm and scalar + scalar addressing modes for the patterns added in https://reviews.llvm.org/D130010


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130993

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

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