[PATCH] D117499: [CodeGen] Support extracting fixed-length vectors from illegal scalable vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

Hi @efriedma,

> The issue would be on a target where a type like v4i1 is legal. i1 vectors are tightly packed in memory, so v1i1, v2i1, v4i1, and v8i1 are all one byte, so you can't just load the part you want.

But if both the result (say a v4i1) and the broken-down input (say a nxv32i1, broken down into nxv16i1) are both legal, then they will both be equally packed in the same way so this should be safe I think? Unless I've misunderstood something it sounds like the problem you're worried about is when the result is packed and the input stored on to the stack is unpacked, right? If so, I don't think I can really write a test case for this because I don't know of any targets that both support scalable vectors and have legal fixed-width predicate vectors. Perhaps I can just add an unreachable for cases like that?


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