[PATCH] D117499: [CodeGen] Support extracting fixed-length vectors from illegal scalable vectors

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Say you're trying to extract a v4i1 from an nxv8i1, with index 4.  If you store the nxv8i1 to the stack, then load it as v4i1, you get the elements at index 0, since the first 8 elements of nxv8i1 are all packed into a single byte.

(Note that SVE doesn't have any native instruction that's equivalent to an nxv2i1/nxv4i1/nxv8i1 store.  Currently, it doesn't come up because nothing emits such operations.)

> I don't think I can really write a test case for this because I don't know of any targets that both support scalable vectors and have legal fixed-width predicate vectors.

True.


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https://reviews.llvm.org/D117499