[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass

Sat Jul 30 15:54:01 PDT 2022

luismarques added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:420
+
+  BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+      .addReg(ScratchReg)
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craig.topper wrote:
> Should preserve the memoperand the call may have had if this is a load? The original expansion was late in the pipe so probably didn't matter. That may be different now that its earlier.
Does the change below address this feedback?

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Comment at: llvm/test/CodeGen/RISCV/mir-target-flags.ll:26-27
 ; RV32-SMALL:      target-flags(riscv-hi) @g_e
+; RV32-SMALL-NEXT: target-flags(riscv-tls-got-hi) @t_un
+; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi0>
 ; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_e
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I tried to add flags to llc to disable any scheduling reorderings but failed to preserve the original order. Any suggestions?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123264/new/

https://reviews.llvm.org/D123264