[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 448865.
luismarques added a comment.

- Add missing initialization/registration of the new pass
- Update the `mir-target-flags.ll` to make it insensitive to the machine-scheduler reorderings that happened once the patch started to preserve the memoperands.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123264/new/

https://reviews.llvm.org/D123264

Files:
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/lib/CodeGen/MachineInstr.cpp
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/elf-preemption.ll
  llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
  llvm/test/CodeGen/RISCV/jumptable.ll
  llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
  llvm/test/CodeGen/RISCV/mir-target-flags.ll
  llvm/test/CodeGen/RISCV/pic-models.ll
  llvm/test/CodeGen/RISCV/tls-models.ll

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