[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1061
+    RVMFI->setBranchRelaxationScratchFrameIndex(MFI.CreateStackObject(
+        RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false));
+  }
----------------
Add this stack object as scavenge frame index in RS. The reason will be explained in the comment below.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1003-1004
+                        &RISCV::GPRRegClass, TRI);
+    TRI->eliminateFrameIndex(std::prev(MI.getIterator()),
+                             /*SpAdj=*/0, /*FIOperandNum=*/1);
+
----------------
piggynl wrote:
> Do we need another spill slot to calculate the offset of the slot in `eliminateFrameIndex`?
> 
if the offset of BranchRelaxationScratchFrameIndex is out of range of `Int<12>`, then an extra scratch register will be created. To avoid this extra scratch register, we need to make sure that the BranchRelaxationScratchFrameIndex is close to the stack base register. Fortunately, PEI will float or sink the scavenge frame index to close to the stack base register(See https://reviews.llvm.org/D89239). But only if BranchRelaxationScratchFrameIndex is a scavenging frame index. 


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  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560