[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1009
+
+  for (auto &C : MF.getConstantPool()->getConstants())
+    FnSize += C.getSizeInBytes(DL);
----------------
ARM places constant pools and jump tables in the middle of functions via the ConstantIslands pass . I don't think we do that on RISC-V. So I think we only need to count instruction size.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560