[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

[Piggy via Phabricator via llvm-commits]

piggynl added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1003-1004
+                        &RISCV::GPRRegClass, TRI);
+    TRI->eliminateFrameIndex(std::prev(MI.getIterator()),
+                             /*SpAdj=*/0, /*FIOperandNum=*/1);
+
----------------
Do we need another spill slot to calculate the offset of the slot in `eliminateFrameIndex`?



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130560/new/

https://reviews.llvm.org/D130560