[PATCH] D130560: [RISCV] Handle register spill in branch relaxation

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When scavenger finds no available register used for "jump" pseudo instruction, spill a register to a stack slot before the jump and restore it after the jump.

Depends on D129999 <https://reviews.llvm.org/D129999>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130560

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/test/CodeGen/RISCV/branch-relaxation-spill-32.ll
  llvm/test/CodeGen/RISCV/branch-relaxation-spill-64.ll
  llvm/test/CodeGen/RISCV/branch-relaxation.ll

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