[PATCH] D129084: [AMDGPU] gfx11 Fix VOP3 dot instructions

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:4199
+  if (TSFlags & SIInstrFlags::IsDOT && TSFlags & SIInstrFlags::VOP3 &&
+      !(TSFlags & SIInstrFlags::VOP3P)) {
+    int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
----------------
dp wrote:
> Is it possible for an opcode to be both `VOP3` and `VOP3P`?
afaik no,  I was surprised that VOP3P instructions also have VOP3 flag, VOP3 instructions don't have VOP3P flag (maybe a bug?). I could check opcodes (I think that there should be 6 opcodes).


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Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:273-274
+class VOP3DotOpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>{
+  let Inst{11} = 0;
+  let Inst{12} = 0;
+}
----------------
dp wrote:
> Bits `op_sel[1:0]` are ignored, so opcodes with these bits set to 1 are legal. Using `?` instead of `0` would allow decoding of such opcodes.
What is desired behavior for 'ignored bits' then?
assembler: report error if op_sel[1:0] are used (sp3 reports error) or parse the 1 and use 0 when printing/encoding instruction
disassembler: read 1 but encode as 0 anyway (sp3 does this) or fail to disassemble  


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129084/new/

https://reviews.llvm.org/D129084