[PATCH] D129084: [AMDGPU] gfx11 Fix VOP3 dot instructions

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:4199
+  if (TSFlags & SIInstrFlags::IsDOT && TSFlags & SIInstrFlags::VOP3 &&
+      !(TSFlags & SIInstrFlags::VOP3P)) {
+    int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
----------------
Is it possible for an opcode to be both `VOP3` and `VOP3P`?


================
Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:273-274
+class VOP3DotOpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>{
+  let Inst{11} = 0;
+  let Inst{12} = 0;
+}
----------------
Bits `op_sel[1:0]` are ignored, so opcodes with these bits set to 1 are legal. Using `?` instead of `0` would allow decoding of such opcodes.


================
Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:1342
+    let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
+    foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in
+      def _e64_gfx11 :
----------------
Looks like this is not necessary.


================
Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:1380-1381
+    def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> {
+      let Inst{11} = 0;
+      let Inst{12} = 0;
+      let DecoderNamespace = "DPPGFX11";
----------------
Ditto.


================
Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:1403-1404
+    def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> {
+      let Inst{11} = 0;
+      let Inst{12} = 0;
+      let DecoderNamespace = "DPP8GFX11";
----------------
Ditto.


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  https://reviews.llvm.org/D129084/new/

https://reviews.llvm.org/D129084