[PATCH] D129084: [AMDGPU] gfx11 Fix VOP3 dot instructions

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/VOPInstructions.td:273-274
+class VOP3DotOpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>{
+  let Inst{11} = 0;
+  let Inst{12} = 0;
+}
----------------
Petar.Avramovic wrote:
> dp wrote:
> > Bits `op_sel[1:0]` are ignored, so opcodes with these bits set to 1 are legal. Using `?` instead of `0` would allow decoding of such opcodes.
> What is desired behavior for 'ignored bits' then?
> assembler: report error if op_sel[1:0] are used (sp3 reports error) or parse the 1 and use 0 when printing/encoding instruction
> disassembler: read 1 but encode as 0 anyway (sp3 does this) or fail to disassemble  
I think that assembler should be strict and report an error if `op_sel[1:0]` bits are not 0. Disassembler should be able to decode instructions with ignored bits to aid in binary code analysis (ignored bits may be displayed as 0 in `op_sel`, this is fine).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129084/new/

https://reviews.llvm.org/D129084