[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:862
+  class LD1RQPat<ValueType vt1, ValueType vt2, SDPatternOperator op, Instruction load_instr, Instruction ptrue> :
+          Pat<(vt1 (op (vt1 (vector_insert_subvec (vt1 undef), (vt2 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
+            (load_instr (ptrue 31), GPR64sp:$Xn, 0)>;
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Looks like an overly large indent. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010