[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 445550.
MattDevereau added a comment.

Dropped `_ldr` from test names and moved `Pat`s into class


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D130010.445550.patch
Type: text/x-patch
Size: 13244 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220718/66c824f0/attachment.bin>