[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

[Matt Devereau via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe0fbd990c9cb: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD (authored by MattDevereau).

Changed prior to commit:
  https://reviews.llvm.org/D130010?vs=445550&id=446423#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll

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