[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

Mon Jul 18 09:26:33 PDT 2022

MattDevereau added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:860-862
+  def : Pat<(nxv16i8 (AArch64duplane128 (nxv16i8 (vector_insert_subvec (nxv16i8 undef), (v16i8 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
+            (LD1RQ_B_IMM (PTRUE_B 31), GPR64sp:$Xn, 0)>;
+  def : Pat<(nxv8i16 (AArch64duplane128 (nxv8i16 (vector_insert_subvec (nxv8i16 undef), (v8i16 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
----------------
paulwalker-arm wrote:
> Is there  a reason not to add the floating point patterns, especially since you've got the tests to show they'll just work?  Also see `LD1RPat` as you likely want to do something similar and I think it's worth having the related logic bunched together.
Discussed offline, this would need a bitcast added to the pattern for the load result and these patterns would be removed by child revision https://reviews.llvm.org/D130013

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010