[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:584-594
-define dso_local <vscale x 2 x double> @dupq_ld1rqd_f64() {
-; CHECK-LABEL: dupq_ld1rqd_f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI49_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI49_0]
-; CHECK-NEXT:    mov z0.q, q0
-; CHECK-NEXT:    ret
----------------
paulwalker-arm wrote:
> See my last comment on D129758, I think you want to keep these to show the need for the later DAG combine?
Discussed offline. It seems all floating point vector splats are being bitcasted from integer vector loads regardless of the input being constant and so these tests are redundant.


================
Comment at: llvm/test/CodeGen/AArch64/sve-ld1r.ll:726
+
+define <vscale x 2 x double> @dupq_ld1rqd_f64_ptr(<2 x double>* %a) {
+; CHECK-LABEL: dupq_ld1rqd_f64_ptr:
----------------
Given we can drop the constant tests entirely, you can drop the `_ptr` from the function names if you want.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010