[PATCH] D130010: [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

Mon Jul 18 07:44:28 PDT 2022

paulwalker-arm added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:860-862
+  def : Pat<(nxv16i8 (AArch64duplane128 (nxv16i8 (vector_insert_subvec (nxv16i8 undef), (v16i8 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
+            (LD1RQ_B_IMM (PTRUE_B 31), GPR64sp:$Xn, 0)>;
+  def : Pat<(nxv8i16 (AArch64duplane128 (nxv8i16 (vector_insert_subvec (nxv8i16 undef), (v8i16 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
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Is there  a reason not to add the floating point patterns, especially since you've got the tests to show they'll just work?  Also see `LD1RPat` as you likely want to do something similar and I think it's worth having the related logic bunched together.

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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:584-594
-define dso_local <vscale x 2 x double> @dupq_ld1rqd_f64() {
-; CHECK-LABEL: dupq_ld1rqd_f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI49_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI49_0]
-; CHECK-NEXT:    mov z0.q, q0
-; CHECK-NEXT:    ret
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See my last comment on D129758, I think you want to keep these to show the need for the later DAG combine?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130010/new/

https://reviews.llvm.org/D130010