[PATCH] D129758: [AArch64][SVE] Lower DUPELANE128 to LD1RQD

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: llvm/include/llvm/Target/TargetSelectionDAG.td:709
+def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
+    SDTypeProfile<1, 3, [SDTCisInt<3>, SDTCisVec<2>, SDTCisVec<1>, SDTCisVec<0>]>,
+    []>;
----------------
I know copied this from extract above but I don't get why the operands are in reverse order?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19195
+
+  SDLoc DL(N);
+
----------------
nit: this can be moved to closer to use (`NewInsert`)


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:6910
+  def : Pat<(vt1 (AArch64duplane128 (vt1 (vector_insert_subvec (vt1 undef), (vt2 (load GPR64sp:$Xn)), (i64 0))), (i64 0))),
+          (!cast<Instruction>(NAME) (pred 31), GPR64sp:$Xn, 0)>;
 }
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nit: align with above pattern


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129758/new/

https://reviews.llvm.org/D129758