[PATCH] D129758: [AArch64][SVE] Lower DUPELANE128 to LD1RQD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19186-19193
+  if (VT == MVT::nxv2f64)
+    NewVT = MVT::nxv2i64;
+  else if (VT == MVT::nxv4f32)
+    NewVT = MVT::nxv4i32;
+  else if (VT == MVT::nxv8f16 || VT == MVT::nxv8bf16)
+    NewVT = MVT::nxv8i16;
+  else
----------------
`NewVT = VT.changeTypeToInteger()`?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19205-19207
+  SDValue Load = Bitcast.getOperand(0);
+  if (Load.getOpcode() != ISD::LOAD)
+    return SDValue();
----------------
Do you need to care what `Bitcast.getOperand(0)` is? I think we're just simplifying the DAG to remove redundant bitcasts to aid isel. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129758/new/

https://reviews.llvm.org/D129758