[PATCH] D129758: [AArch64][SVE] Lower DUPELANE128 to LD1RQD

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 444647.
MattDevereau added a comment.

Following an offline talk, ld1rqd/w/h/s needs to respect the original width of the load type due to big endian targets


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129758/new/

https://reviews.llvm.org/D129758

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

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