[PATCH] D129758: [AArch64][SVE] Lower DUPELANE128 to LD1RQD

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau created this revision.
MattDevereau added reviewers: peterwaller-arm, paulwalker-arm, c-rhodes, bsmith, dtemirbulatov, david-arm.
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Following on from https://reviews.llvm.org/D128902, lower DUPLANE128 to LD1RQD. This also introduces some DAGCombine logic to simplify bitcasts out of loading logic to result in less logically redundant patterns being added to instruction selection


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129758

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

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