[PATCH] D129637: [AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel
Joe Nash via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 13 07:01:34 PDT 2022
Joe_Nash added a comment.
Overall this is a good patch, thanks for identifying the issue. It will also help towards https://reviews.llvm.org/D129084. See inline.
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Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:752
+static unsigned getOpSel(const MCInst &MI) {
+ unsigned Opc = MI.getOpcode();
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This is a very similar to the code in convertVOP3PDPP. Can we de-duplicate it and create a helper function that collects all modifier values?
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Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:761
+ if (OpIdx == -1)
+ break;
+ unsigned Val = MI.getOperand(OpIdx).getImm();
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Can we make this generic over instructions that don't have modifiers on certain operands (e.g. DOT2_BF16_BF16) by changing break to continue?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D129637/new/
https://reviews.llvm.org/D129637
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