[PATCH] D129580: [PowerPC][LLD] Change the behavior of the PPC64R2SaveStub thunk.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei.
Herald added subscribers: shchenz, kbarton, arichardson, emaste.
Herald added a reviewer: MaskRay.
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stefanp requested review of this revision.
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Currently the PPC64R2SaveStub thunk will produce Power 10 code by default.
This produced an issue when linking older code that made use of the st_other=1
bit but was never meant to be linked or run on Power 10. When lld added the
R2 <https://reviews.llvm.org/source/clang-tools-extra/> Save Stub to that code at link time previous code that was runable on
Power 8 now included Power 10 code.

This patch makes it so that only the R_PPC64_REL24_NOTOC relocation can produce
Power 10 code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129580

Files:
  lld/ELF/Thunks.cpp
  lld/test/ELF/ppc64-toc-call-to-pcrel-long-jump.s


Index: lld/test/ELF/ppc64-toc-call-to-pcrel-long-jump.s
===================================================================
--- lld/test/ELF/ppc64-toc-call-to-pcrel-long-jump.s
+++ lld/test/ELF/ppc64-toc-call-to-pcrel-long-jump.s
@@ -13,7 +13,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64le %t/asm -o %t.o
 # RUN: ld.lld -T %t/lts %t.o -o %t_le --no-power10-stubs
-# RUN: llvm-objdump --mcpu=pwr10 --no-show-raw-insn -d %t_le | FileCheck %s --check-prefix=NoP10
+# RUN: llvm-objdump --mcpu=pwr10 --no-show-raw-insn -d %t_le | FileCheck %s
 # RUN: llvm-readelf -s %t_le | FileCheck %s --check-prefix=SYM
 
 # SYM:      Symbol table '.symtab' contains 9 entries:
@@ -74,20 +74,11 @@
 # CHECK-NEXT:    blr
 # CHECK-LABEL: <__toc_save_callee>:
 # CHECK:         std 2, 24(1)
-# CHECK-NEXT:    paddi 12, 0, -268501028, 1
+# CHECK-NEXT:    addis 12, 2, -4098
+# CHECK-NEXT:    addi 12, 12, 32704
 # CHECK-NEXT:    mtctr 12
 # CHECK-NEXT:    bctr
 
-# NoP10-LABEL: <caller>:
-# NoP10:         bl 0x20020020
-# NoP10-NEXT:    ld 2, 24(1)
-# NoP10-NEXT:    blr
-# NoP10-LABEL: <__toc_save_callee>:
-# NoP10-NEXT:         std 2, 24(1)
-# NoP10-NEXT:    addis 12, 2, -4098
-# NoP10-NEXT:    addi 12, 12, 32704
-# NoP10-NEXT:    mtctr 12
-# NoP10-NEXT:    bctr
 .section .text_caller, "ax", %progbits
 .Lfunc_toc2:
   .quad .TOC.-.Lfunc_gep2
Index: lld/ELF/Thunks.cpp
===================================================================
--- lld/ELF/Thunks.cpp
+++ lld/ELF/Thunks.cpp
@@ -916,25 +916,18 @@
     write32(buf + 4, 0x48000000 | (offset & 0x03fffffc)); // b    <offset>
   } else if (isInt<34>(offset)) {
     int nextInstOffset;
-    if (!config->power10Stubs) {
-      uint64_t tocOffset = destination.getVA() - getPPC64TocBase();
-      if (tocOffset >> 16 > 0) {
-        const uint64_t addi = ADDI_R12_TO_R12_NO_DISP | (tocOffset & 0xffff);
-        const uint64_t addis = ADDIS_R12_TO_R2_NO_DISP | ((tocOffset >> 16) & 0xffff);
-        write32(buf + 4, addis); // addis r12, r2 , top of offset
-        write32(buf + 8, addi);  // addi  r12, r12, bottom of offset
-        nextInstOffset = 12;
-      } else {
-        const uint64_t addi = ADDI_R12_TO_R2_NO_DISP | (tocOffset & 0xffff);
-        write32(buf + 4, addi); // addi r12, r2, offset
-        nextInstOffset = 8;
-      }
-    } else {
-      const uint64_t paddi = PADDI_R12_NO_DISP |
-                             (((offset >> 16) & 0x3ffff) << 32) |
-                             (offset & 0xffff);
-      writePrefixedInstruction(buf + 4, paddi); // paddi r12, 0, func at pcrel, 1
+    uint64_t tocOffset = destination.getVA() - getPPC64TocBase();
+    if (tocOffset >> 16 > 0) {
+      const uint64_t addi = ADDI_R12_TO_R12_NO_DISP | (tocOffset & 0xffff);
+      const uint64_t addis =
+          ADDIS_R12_TO_R2_NO_DISP | ((tocOffset >> 16) & 0xffff);
+      write32(buf + 4, addis); // addis r12, r2 , top of offset
+      write32(buf + 8, addi);  // addi  r12, r12, bottom of offset
       nextInstOffset = 12;
+    } else {
+      const uint64_t addi = ADDI_R12_TO_R2_NO_DISP | (tocOffset & 0xffff);
+      write32(buf + 4, addi); // addi r12, r2, offset
+      nextInstOffset = 8;
     }
     write32(buf + nextInstOffset, MTCTR_R12); // mtctr r12
     write32(buf + nextInstOffset + 4, BCTR);  // bctr


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